Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 111

Burst ROM read cycle
SRAM read cycle
BCLK
t
AD
A[23:2]
t
AD
A[1:0]
t
CE1
#CEx
#RD
t
ACC2
t
CEAC
t
RDAC2
D[15:0]
t
1 is measured with respect to the first signal change (negation) from among the #RD, #CEx and
RDH
A[23:0] signals.
#BUSREQ, #BUSACK and #NMI timing
BCLK
#BUSREQ
#BUSACK
eBUS_OUT signals 1
eBUS_OUT signals 1
#NMI
1 eBUS_OUT indicates the following pins:
A[23:0], #RD, #WRL, #WRH, #HCAS, #LCAS, #CE[17:4], D[15:0]
Input, output and I/O port timing
BCLK
Kxx, Pxx
(input: data read
from the port)
Pxx, Rxx (output)
Kxx
(K-port interrupt input)
S1C33L03 PRODUCT PART
Burst cycle
t
AD
t
RDD1
t
ACCB
t t
RDS RDS
t
RDH
t
BRQS
Valid input
t
INPS
Valid input
EPSON
8 ELECTRICAL CHARACTERISTICS
Burst cycle Burst cycle
t t
AD AD
t t
ACCB ACCB
t
RDS
t t
RDH RDH
t
BRQH
t
BAKD
t
Z2E
t
B2Z
t
NMIW
t
INPH
t
OUTD
t
KINW
t
AD
t
AD
t
CE2
t
RDD2
t
RDS
1
t
RDH
A-95
A-1
A-8