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VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Register name
Address
Bit
Bus control
004812E
DF
register
(HW)
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DRAM timing
0048130
DF–C
set-up register
(HW)
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Access control
0048132
DF
register
(HW)
DE
DD
DC
DB
DA
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
B-VI-2-24
Name
Function
RBCLK
BCLK output control
–
reserved
RBST8
Burst ROM burst mode selection
REDO
DRAM page mode selection
RCA1
Column address size selection
RCA0
RPC2
Refresh enable
RPC1
Refresh method selection
RPC0
Refresh RPC delay setup
RRA1
Refresh RAS pulse width
RRA0
selection
–
reserved
SBUSST
External interface method selection
SEMAS
External bus master setup
SEPD
External power-down control
SWAITE
#WAIT enable
–
reserved
A3EEN
Area 3 emulation
CEFUNC1
#CE pin function selection
CEFUNC0
CRAS
Successive RAS mode setup
RPRC1
DRAM
RPRC0
RAS precharge cycles selection
–
reserved
CASC1
DRAM
CASC0
CAS cycles selection
–
reserved
RASC1
DRAM
RASC0
RAS cycles selection
A18IO
Area 18, 17 internal/external access
A16IO
Area 16, 15 internal/external access
A14IO
Area 14, 13 internal/external access
A12IO
Area 12, 11 internal/external access
–
reserved
A8IO
Area 8, 7 internal/external access
A6IO
Area 6 internal/external access
A5IO
Area 5, 4 internal/external access
A18EC
Area 18, 17 endian control
A16EC
Area 16, 15 endian control
A14EC
Area 14, 13 endian control
A12EC
Area 12, 11 endian control
A10EC
Area 10, 9 endian control
A8EC
Area 8, 7 endian control
A6EC
Area 6 endian control
A5EC
Area 5, 4 endian control
Setting
1 Fixed at H
0 Enabled
–
1 8-successive 0 4-successive
1 EDO
0 Fast page
RCA[1:0]
1
1
1
0
0
1
0
0
1 Enabled
0 Disabled
1 Self-refresh 0 CBR-refresh
1 2.0
0 1.0
RRA[1:0]
Number of cycles
1
1
1
0
0
1
0
0
–
1 #BSL
0 A0
1 Existing
0 Nonexistent
1 Enabled
0 Disabled
1 Enabled
0 Disabled
–
1 Internal ROM 0 Emulation
CEFUNC[1:0]
#CE output
1
x
#CE7/8..#CE17/18
0
1
#CE6..#CE17
0
0
#CE4..#CE10
1 Successive 0 Normal
RPRC[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
CASC[1:0] Number of cycles
1
1
1
0
0
1
0
0
–
RASC[1:0] Number of cycles
1
1
1
0
0
1
0
0
1 Internal
0 External
access
access
–
1 Internal
0 External
access
access
1 Big endian
0 Little endian
EPSON
Init. R/W
Remarks
0
R/W
0
–
Writing 1 not allowed.
0
R/W
0
R/W
Size
0
R/W
11
0
10
9
8
0
R/W
0
R/W
0
R/W
0
R/W
5
0
4
3
2
0
–
Writing 1 not allowed.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
1
R/W
0
R/W
0
0
R/W
0
R/W
4
0
3
2
1
–
–
0 when being read.
0
R/W
4
0
3
2
1
–
–
0 when being read.
0
R/W
4
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
S1C33L03 FUNCTION PART
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