Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 203

Refresh RPC delay
Use RPC0 to set the RPC delay value of a refresh cycle (a delay time from the immediately preceding
precharge to the fall of #CAS).
RPC0 = "1": 2 cycles
RPC0 = "0": 1 cycle
Refresh RAS pulse width
Use RRA to set the #RAS pulse width of a CAS-before-RAS refresh cycle.
The initial default value is 2 cycles.
Number of RAS precharge cycles
Use RPRC to choose the number of RAS precharge cycles.
The initial default value is 1 cycle.
CAS cycle control
Use CASC to choose the number of CAS cycles when accessing DRAM.
The initial default value is 1 cycle.
RAS cycle control
Use RASC to choose the number of RAS cycles when accessing DRAM.
The initial default value is 1 cycle.
S1C33L03 FUNCTION PART
Table 4.19 Refresh RAS Pulse Width
RRA1 RRA0 Pulse width
1 1
1 0
0 1
0 0
Table 4.20 Number of RAS Precharge Cycles
RPRC1 RPRC0 Number of cycles
1 1
1 0
0 1
0 0
Table 4.21 Number of CAS Cycles
CASC1 CASC0 Number of cycles
1 1
1 0
0 1
0 0
Table 4.22 Number of RAS Cycles
RASC1 RASC0 Number of cycles
1 1
1 0
0 1
0 0
EPSON
II CORE BLOCK: BCU (Bus Control Unit)
5 cycles
4 cycles
3 cycles
2 cycles
4 cycles
3 cycles
2 cycles
1 cycle
4 cycles
3 cycles
2 cycles
1 cycle
4 cycles
3 cycles
2 cycles
1 cycle
A-1
B-II
BCU
B-II-4-27