Clock - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Clock

The LCD controller uses the BCU clock as the source clock for its pixel clock PCLK and display memory clock
MCLK. The maximum clock frequency that can be supplied to the LCD controller is 25 MHz. The BCU clock
divide ratios can be set using the LCLKSEL[2:0] (D[2:0])/FIFO control register (0x39FFF4), as shown in Table
2.3 below.
CLG
CPU_CLK
LCLKSEL2
0
0
0
0
1
1
1
1
S1C33L03 FUNCTION PART
#X2SPD pin
BCU
BCU_CLK
1/1 or 1/2
Figure 2.3 LCDC Clocks
Table 2.3 Selection of LCDC Clocks
LCLKSEL1 LCLKSEL0
0
0
1
1
0
0
1
1
EPSON
VII LCD CONTROLLER BLOCK: LCD CONTROLLER
To CPU
Bus clock
LCLKSEL[2:0]
1/1
1/2
LCDC clock (PCLK, MCLK)
1/3
1/4
LCDC clock
0 Turned off
1 Turned off
0 Turned off
1 Reserved (not allowed)
0 BCU_CLK
1 BCU_CLK/2
0 BCU_CLK/3
1 BCU_CLK/4
A-1
B-VII
LCDC
B-VII-2-7