Bus Cycles In External System Interface; Sram Read Cycles - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Bus Cycles in External System Interface

The following shows a sample SRAM connection the basic bus cycles.
S1C33
A[9:1]
D[15:0]
#RD
#WRH
#WRL
#CE
(1) A0 system (little endian/big endian)

SRAM Read Cycles

Basic read cycle with no wait mode
Read cycle with wait mode
Example: When the BCU has no internal wait mode and 2 wait cycles via #WAIT pin are inserted
BCLK
A[23:0]
#CExx
D[15:0]
#RD
#WAIT
The #WAIT signal is sampled at the falling edge of the transition of BCLK (bus clock) and when it is
sampled on an inactive (high level), the read cycle is terminated.
Note: Insertion of wait cycles via the #WAIT pin is possible only when the device for bus conditions is set
for SRAM, and SWAITE (D0) / Bus control register (0x4812E) is enabled for waiting.
S1C33L03 FUNCTION PART
SRAM S1C33
A[8:0] A[9:1]
I/O[15:0] D[15:0]
#RD A0
#WRH #WRH
#WRL #WRL
#CE #CE
#RD
(2) #BSL system (little endian)
Figure 4.18 Sample DRAM Connection
BCLK
A[23:0]
#CExx
D[15:0]
#RD
#WAIT
Figure 4.19 Basic Read Cycle with No Wait
C1
Figure 4.20 Read Cycle with Wait
EPSON
II CORE BLOCK: BCU (Bus Control Unit)
SRAM S1C33
A[8:0] A[9:1]
I/O[15:0] D[15:0]
#LB A0
#UB #WRH
#WE #WRL
#OS #CE
#OE #RD
(3) #BSL system (big endian)
C1
addr
data
CW CW
addr
data
A-1
SRAM
A[8:0]
I/O[15:0]
#LB
#UB
#WE
#OS
#OE
B-II
BCU
B-II-4-19