Idma Invocation - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

IDMA Invocation

The triggers by which IDMA is invoked have the following three causes:
1. Interrupt factor in an internal peripheral circuit
2. Trigger in the software application
3. Link setting
Enabling/disabling DMA transfer
The IDMA controller is enabled by writing "1" to the IDMA enable bit IDMAEN (D0) / IDMA enable
register (0x48205), and is ready to accept the triggers described above. However, before enabling a DMA
transfer, be sure to set the base address and the control information for the channel to be invoked correctly. If
IDMAEN is set to "0", no IDMA invocation request is accepted.
IDMA invocation by an interrupt factor in internal peripheral circuits
Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by an interrupt
factor in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are predetermined.
The relationship between the interrupt factors that have this function and the IDMA channels is shown in
Table 3.2.
Peripheral circuit
Ports Port input 0
Port input 1
Port input 2
Port input 3
High-speed DMA Ch.0, end of transfer
Ch.1, end of transfer
16-bit programmable Timer 0 comparison B
timer Timer 0 comparison A
Timer 1 comparison B
Timer 1 comparison A
Timer 2 comparison B
Timer 2 comparison A
Timer 3 comparison B
Timer 3 comparison A
Timer 4 comparison B
Timer 4 comparison A
Timer 5 comparison B
Timer 5 comparison A
8-bit programmable Timer 0 underflow
timer Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Serial interface Ch.0 receive buffer full
Ch.0 transmit buffer empty
Ch.1 receive buffer full
Ch.1 transmit buffer empty
A/D converter End of A/D conversion
Ports Port input 4
Port input 5
Port input 6
Port input 7
S1C33L03 FUNCTION PART
Table 3.2 Interrupt Factors Used to Invoke IDMA
Interrupt factor IDMA Ch.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EPSON
V DMA BLOCK: IDMA (Intelligent DMA)
IDMA request bit
RP0 (D0/0x40290) DEP0 (D0/0x40294)
RP1 (D1/0x40290) DEP1 (D1/0x40294)
RP2 (D2/0x40290) DEP2 (D2/0x40294)
RP3 (D3/0x40290) DEP3 (D3/0x40294)
RHDM0 (D4/0x40290) DEHDM0 (D4/0x40294)
RHDM1 (D5/0x40290) DEHDM1 (D5/0x40294)
R16TU0 (D6/0x40290) DE16TU0 (D6/0x40294)
R16TC0 (D7/0x40290) DE16TC0 (D7/0x40294)
R16TU1 (D0/0x40291) DE16TU1 (D0/0x40295)
R16TC1 (D1/0x40291) DE16TC1 (D1/0x40295)
R16TU2 (D2/0x40291) DE16TU2 (D2/0x40295)
R16TC2 (D3/0x40291) DE16TC2 (D3/0x40295)
R16TU3 (D4/0x40291) DE16TU3 (D4/0x40295)
R16TC3 (D5/0x40291) DE16TC3 (D5/0x40295)
R16TU4 (D6/0x40291) DE16TU4 (D6/0x40295)
R16TC4 (D7/0x40291) DE16TC4 (D7/0x40295)
R16TU5 (D0/0x40292) DE16TU5 (D0/0x40296)
R16TC5 (D1/0x40292) DE16TC5 (D1/0x40296)
R8TU0 (D2/0x40292) DE8TU0 (D2/0x40296)
R8TU1 (D3/0x40292) DE8TU1 (D3/0x40296)
R8TU2 (D4/0x40292) DE8TU2 (D4/0x40296)
R8TU3 (D5/0x40292) DE8TU3 (D5/0x40296)
RSRX0 (D6/0x40292) DESRX0 (D6/0x40296)
RSTX0 (D7/0x40292) DESTX0 (D7/0x40296)
RSRX1 (D0/0x40293) DESRX1 (D0/0x40297)
RSTX1 (D1/0x40293) DESTX1 (D1/0x40297)
RADE (D2/0x40293) DEADE (D2/0x40297)
RP4 (D4/0x40293) DEP4 (D4/0x40297)
RP5 (D5/0x40293) DEP5 (D5/0x40297)
RP4 (D6/0x40293) DEP4 (D6/0x40297)
RP7 (D7/0x40293) DEP7 (D7/0x40297)
A-1
IDMA enable bit
B-V
IDMA
B-V-3-5