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II CORE BLOCK: CPU AND OPERATING MODE
Trap Table
Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of
exceptions and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts.
Serial interface Ch.2 and Ch.3 interrupts share the trap table for port input interrupts and 16-bit timer interrupts.
Refer to Section III-8, "Serial Interface", for details of the settings.
HEX
Vector number
Exception/interrupt name
No.
(Hex address)
0
0(Base)
Reset
1–3
reserved
4
4(Base+10)
Zero division
5
5
reserved
6
6(Base+18)
Address error exception
7
0x0 or 0x60000 Debugging exception
8
8(Base+1C)
NMI
9–11
reserved
C
12(Base+30)
Software exception 0
D
13(Base+34)
Software exception 1
E
14(Base+38)
Software exception 2
F
15(Base+3C)
Software exception 3
10
16(Base+40)
Port input interrupt 0
11
17(Base+44)
Port input interrupt 1
12
18(Base+48)
Port input interrupt 2
13
19(Base+4C)
Port input interrupt 3
14
20(Base+50)
Key input interrupt 0
15
21(Base+54)
Key input interrupt 1
16
22(Base+58)
High-speed DMA Ch.0
17
23(Base+5C)
High-speed DMA Ch.1
18
24(Base+60)
High-speed DMA Ch.2
19
25(Base+64)
High-speed DMA Ch.3
1A
26(Base+68)
IDMA
27–29
reserved
1E
30(Base+78)
16-bit programmable timer 0
1F
31(Base+7C)
32–33
reserved
22
34(Base+88)
16-bit programmable timer 1
23
35(Base+8C)
36–37
reserved
26
38(Base+98)
16-bit programmable timer 2
27
39(Base+9C)
40–41
reserved
2A
42(Base+A8)
16-bit programmable timer 3
2B
43(Base+AC)
44–45
reserved
2E
46(Base+B8)
16-bit programmable timer 4
2F
47(Base+BC)
48–49
reserved
32
50(Base+C8)
16-bit programmable timer 5
33
51(Base+CC)
34
52(Base+D0)
8-bit programmable timer
35
53(Base+D4)
36
54(Base+D8)
37
55(Base+DC)
B-II-2-4
Table 2.1 Trap Table
Exception/interrupt factor
Low input to the reset pin
–
Division instruction
–
Memory access instruction
brk instruction, etc.
Low input to the NMI pin
–
int instruction
int instruction
int instruction
int instruction
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Edge (rising or falling) or level (High or Low)
Rising or falling edge
Rising or falling edge
High-speed DMA Ch.0, end of transfer
High-speed DMA Ch.1, end of transfer
High-speed DMA Ch.2, end of transfer
High-speed DMA Ch.3, end of transfer
Intelligent DMA, end of transfer
–
Timer 0 comparison B
Timer 0 comparison A
–
Timer 1 comparison B
Timer 1 comparison A
–
Timer 2 comparison B
Timer 2 comparison A
–
Timer 3 comparison B
Timer 3 comparison A
–
Timer 4 comparison B
Timer 4 comparison A
–
Timer 5 comparison B
Timer 5 comparison A
Timer 0 underflow
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
EPSON
IDMA
Priority
Ch.
–
High
–
–
–
–
–
–
–
–
–
–
–
1
2
3
4
–
–
5
6
–
–
–
–
7
8
–
9
10
–
11
12
–
13
14
–
15
16
–
17
18
19
20
21
22
Low
S1C33L03 FUNCTION PART
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