Single Read/Single Write - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Figure 2.12 shows an example of a timing chart in cases where the row address is varied during burst read.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]

Single Read/Single Write

If the burst length is set to "1" (SDRBL[1:0] = "00"), the SDRAM controller reads data from the SDRAM in a
single operation.
When writing to the SDRAM, data are always written in a single operation, no matter what burst length is selected.
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
BCLK
Command
SDCKE
#SDCEx
#SDRAS
#SDCAS
#SDWE
SDBA[1:0]
SDA[10]
SDA[12:11, 9:0]
LDQM/HDQM
DQ[15:0]
B-VI-2-16
NOP PRE NOP ACTV NOP READ
H
BA BA BA
ROW1
ROW1 COLn
t t
CAS latency
RP RCD
t
Figure 2.12 Changing Row Address During Burst Read
NOP PRE NOP ACTV
H
BA1 BA1
ROW1
ROW1
t
RP
Figure 2.13 Single Read to Single Write (different page)
NOP PRE NOP ACTV
H
BA BA
ROW1
ROW1
t
RP
Figure 2.14 Burst Read to Single Write (same page)
NOP PRE NOP ACTV NOP
BA BA
ROW2
ROW2
D D D
(n) (n+1) (n+2)
t t
RP RCD
= 2
RAS
NOP READ NOP PRE NOP ACTV NOP
BA1 BA2
ROW2
COL1 ROW2
D
(1)
t t
CAS latency
RCD RP
= 2
NOP READ NOP
BA
COLn
D D D
(n) (n+1) (n+2)
t
CAS latency
RCD
= 2
EPSON
READ NOP
BA
COL0
D D D
(0) (1) (2)
CAS latency
= 2
WRIT
BA2 BA2
COL2
D
(2)
t
RCD
WRIT NOP PRE NOP
BA BA
COLm
D
(m)
S1C33L03 FUNCTION PART