Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 403

Selecting input pins
For the FPK1 interrupt system, a four-bit input pin group can be selected from the four predefined groups.
For the FPK0 system, a five-bit input pin group can be selected.
Table 9.7 shows the control bits and the selectable groups for each factor.
Interrupt
factor
FPK1 SPPK1[1:0] (D[3:2])/Key input interrupt select register (0x402CA)
FPK0 SPPK0[1:0] (D[1:0])/Key input interrupt select register (0x402CA)
Conditions for key input-interrupt generation
The key input interrupt circuit has two input mask registers (SMPK0[4:0] for FPK0 and SMPK1[3:0] for
FPK1) and two input comparison registers (SCPK0[4:0] for FPK0 and SCPK0[3:0] for FPK1) to set input-
interrupt conditions.
The input mask register SMPK is used to mask the input pin that is not used for an interrupt. This register
masks each input pin, whereas the interrupt enable register of the interrupt controller masks the interrupt
factor for each interrupt group.
The input comparison register SCPK is used to select whether an interrupt for each input port is to be
generated at the rising or falling edge of the input.
A change in state occurs so that the input pin enabled for interrupt by the interrupt mask register SMPK and
the content of the input comparison register SCPK become unmatched after being matched, the interrupt
factor flag FK is set to "1" and, if other interrupt conditions are met, an interrupt is generated.
Figure 9.5 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the K5[4:0] pins are
selected for the input-pin group and the control register of the interrupt controller is set so as to enable
generation of a FPK0 interrupt.
Intput mask register SMPK0
SMPK04 SMPK03
1
Input comparison register SCPK0
SCPK04 SCPK03
1
With the settings shown above, FPK0 interrupt is generated under the condition shown below.
(1)
K54 K53
1
(2)
K54 K53
1
(3)
K54 K53
1
(4)
K54 K53
1
Figure 9.5 FPK0 Interrupt Generation Example (when K5[4:0] is selected by SPPK[1:0])
S1C33L03 FUNCTION PART
Table 9.7 Selecting Pins for Key Input Interrupts
Control bit
SMPK02 SMPK01 SMPK00
1 1 1
SCPK02 SCPK01 SCPK00
1 0 1
Input port K5
K52 K51
1 0 1
K52 K51
1 0 1
K52 K51
0 0 1
K52 K51
0 1 1
III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
P2[7:4] P0[7:4]
P2[4:0] P0[4:0]
0
0
K50
(Initial value)
0
K50
1
K50
0
Interrupt generation
Because interrupt has been disabled for
K50, interrupt will be generated when non-
K50
conformity occurs between the contents of
0
the four bits K51–K54 and the four bits
input comparison register SCPK0[4:1].
EPSON
SPPK settings
11 10 01
K6[7:4] K6[3:0]
K6[4:0] K5[4:0]
B-III-9-15
A-1
00
B-III
I/O