Serial Interface; Configuration Of Serial Interfaces; Features Of Serial Interfaces - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Cmos 32-bit single chip microcomputer
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III-8 SERIAL INTERFACE

Configuration of Serial Interfaces

Features of Serial Interfaces

The Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which
are described below. The functions of these four serial interfaces are the same.
• A clock-synchronized or asynchronous mode can be selected for the transfer method.
Clock-synchronized mode
Data length:
8 bits, fixed (No start, stop, and parity bits)
Receive error: An overrun error can been detected.
Asynchronous mode
Data length:
7 or 8 bits, selectable
Receive error: Overrun, framing, or parity errors can been detected.
Start bit:
1 bit, fixed
Stop bit:
1 or 2 bits, selectable
Parity bit:
Even, odd, or none; selectable
Since the transmit and receive units are independent, full-duplex communication is possible.
• Baud-rate setting: Any desired baud rate can be set by selecting the prescaler's division ratio, setting the 8-bit
programmable timer, or using external clock input (asynchronous mode only).
• The receive and transmit units are constructed with a double-buffer structure, allowing for successive receive and
transmit operations.
• Data transfers using IDMA or HSDMA are possible.
• Three types of interrupts (transmit data empty, receive data full, and receive error) can be generated.
Figure 8.1 shows the configuration of the serial interface (one channel).
Control registers
Serial output
SOUTx
control circuit
Serial input
SINx
control circuit
#SCLKx
Note: Ch.0 to Ch.3 have the same configuration and the same function. The signal and control bit
names are suffixed by a 0, 1, 2, or 3 to indicate the channel number, enabling discrimination
between channels 0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with "x"
unless discrimination is necessary, because explanations are common to all four channels.
S1C33L03 FUNCTION PART
Internal data bus
Transmit unit
Receive unit
Data buffer
Data buffer
and
and
shift register
shift register
Start bit
Clock
detection circuit
control circuit
Figure 8.1 Configuration of Serial Interface
EPSON
III PERIPHERAL BLOCK: SERIAL INTERFACE
Transmit data buffer empty
interrupt request
Interrupt
Receive data buffer full
control circuit
interrupt request
Receive error
interrupt request
Ready signal
#SRDYx
control circuit
8-bit programmable timer output
A-1
B-III
SIF
B-III-8-1

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