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Combination of System Bus Control Signals
The bus control signal pins that have two or more functions have their functionality determined when an interface
method is selected by a program. The BCU contains an ordinary external system interface (two interface method
are supported) and a DRAM interface.
Interface type
External system interface
DRAM interface
SBUSST is initialized to "0" at cold start.
When the IC is hot-started, these bits retain their status before the chip was reset.
Table 4.4 shows combinations of control signals classified by each interface method.
1 In the #BSL system, the A0 and #WRH pin functions change according to the endian selected (little endian
or big endian).
When using DRAM, the #CE output pins in areas 7–8 (areas 13–14) function as the #RAS1–2 (#RAS3–4)
pins.
S1C33L03 FUNCTION PART
Table 4.3 Interface Selection
Interface method
A0 system (default)
#BSL system
2CAS system (fixed)
Table 4.4 Combinations of Bus Control Signals
External system interface
A0 system
#BSL system
A0
#BSL (little endian) /
#BSH (big endian) 1
#WRL
#WR
#WRH
#BSH (little endian) /
#BSL (big endian) 1
–
–
–
–
#CEx
#CEx
EPSON
II CORE BLOCK: BCU (Bus Control Unit)
Control bit
SBUSST(D3/0x4812E) = "0"
SBUSST(D3/0x4812E) = "1"
None
DRAM interface
2CAS system
–
#WE
–
#HCAS
#LCAS
#RASx 2
A-1
B-II
BCU
B-II-4-3
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