Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 465

Register name Address Bit
High-speed 004825A DF
DMA Ch.3 (HW) DE
high-order
destination
address set-up
register DD
DC
Note:
D) Dual address
mode
S) Single
DB
address
DA
mode
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
High-speed 004825C DF–1
DMA Ch.3 (HW)
enable register D0
High-speed 004825E DF–1
DMA Ch.3 (HW)
trigger flag D0
register
CFK51–CFK50: K5[1:0] pin function selection (D[1:0]) / K5 function select register (0x402C0)
CFK54–CFK53: K5[4:3] pin function selection (D[4:3]) / K5 function select register (0x402C0)
Set the #DMAREQx pin of HSDMA.
Write "1": #DMAREQx input
Write "0": Input port
Read: Valid
CFK50, CFK51, CFK53 and CFK54 are the function select bits for K50 (#DMAREQ0), K51 (#DMAREQ1), K53
(#DMAREQ2) and K54 (#DMAREQ3), respectively. When using the #DMAREQx signal, write "1" to CFK5x to
set the K5x port for inputting the signal.
If this bit is set to "0", the pin is set for an input port.
At cold start, CFK5x is set to "0" (input port). At hot start, CFK5x retains the previous status before an initial reset.
CFP16–CFP15: P1[6:5] pin function selection (D[6:5]) / P1 function select register (0x402D4)
Set the #DMAENDx pin of HSDMA.
Write "1": #DMAENDx output
Write "0": I/O port
Read: Valid
When using the #DMAEND0 signal, set the P15 pin for the #DMAEND0 output pin by writing "1" to CFP15.
Similarly, when using the #DMAEND1 signal, set the P16 pin for the #DMAEND1 output pin by writing "1" to
CFP16. Furthermore, direct these pins for output by writing "1" to the corresponding I/O control register.
If CFP1x is set to "0", the pin is set for an I/O port.
At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset.
S1C33L03 FUNCTION PART
Name Function
D3MOD1 Ch.3 transfer mode
D3MOD0
D3IN1 D) Ch.3 destination address
D3IN0 control
S) Invalid
D3ADRH11 D) Ch.3 destination
D3ADRH10 address[27:16]
D3ADRH9 S) Invalid
D3ADRH8
D3ADRH7
D3ADRH6
D3ADRH5
D3ADRH4
D3ADRH3
D3ADRH2
D3ADRH1
D3ADRH0
– reserved
HS3_EN Ch.3 enable
– reserved
HS3_TF Ch.3 trigger flag clear (writing)
Ch.3 trigger flag status (reading)
EPSON
V DMA BLOCK: HSDMA (High-Speed DMA)
Setting Init. R/W
D3MOD[1:0] Mode 0
1 1 Invalid 0
1 0 Block
0 1 Successive
0 0 Single
D3IN[1:0] Inc/dec 0
1 1 Inc.(no init) 0
1 0 Inc.(init)
0 1 Dec.(no init)
0 0 Fixed
X
X
X
X
X
X
X
X
X
X
X
X
– –
1 Enable 0 Disable 0
– –
1 Clear 0 No operation 0
1 Set 0 Cleared
A-1
Remarks
R/W
R/W
R/W
– Undefined in read.
R/W
– Undefined in read.
R/W
B-V
HSDMA
B-V-2-27