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I-3 LIST OF PINS
List of External I/O Pins
The following lists the external I/O pins of the C33 Core Block, Peripheral Block and LCD Controller Block. Note
that some pins are listed in two or more tables.
Pin name
Pin No.
I/O
A0
85
O
#BSL
A[10:1]
85–90,92–96
O
SDA[9:0]
A11
97
O
A[13:12]
99,100
O
SDA[12:11]
A[15:14]
101,102
O
SDBA[1:0]
A[23:16]
103,104,
O
106–111
D[15:0]
46–50,52–58,
I/O
60–63
#CE10EX
137
O
#CE9&10EX
#CE9
131
O
#CE17
#CE17&18
#CE8
64
O
#RAS1
#CE14
#RAS3
#SDCE1
#CE7
65
O
#RAS0
#CE13
#RAS2
#SDCE0
#CE6
138
O
#CE7&8
#CE5
133
O
#CE15
#CE15&16
#CE4
139
O
#CE11
#CE11&12
#CE3
135
O
#RD
44
O
#EMEMRD
126
O
#WRL
43
O
#WR
#WE
#WRH
42
O
#BSH
S1C33L03 FUNCTION PART
Table 3.1 List of Pins for External Bus Interface Signals
Pull-up
–
A0:
Address bus (A0) when SBUSST(D3/0x4812E) = "0" (default)
#BSL:
Bus strobe (low byte) signal when SBUSST(D3/0x4812E) = "1"
A[10:1]:
Address bus (A1–A10)
–
SDA[9:0]:
SDRAM address bus (SDA0–SDA9)
–
Address bus (A11)
–
A[13:12]:
Address bus (A12–A13)
SDA[12:11]: SDRAM address bus (SDA11–SDA12)
–
A[15:14]:
Address bus (A14–A15)
SDBA[1:0]: SDRAM bank select (SDBA0–SDBA1)
–
Address bus (A16–A23)
–
Data bus (D0–D15)
–
Area 10 chip enable for external memory
* When CEFUNC[1:0] = "1x", this pin outputs #CE9+#CE10EX signal.
–
#CE9:
Area 9 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE17:
Area 17 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE17+#CE18 signal.
–
#CE8:
Area 8 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "0" and SDRPC1(D2/0x39FFC0) = "0" (default)
#RAS1:
Area 8 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A8DRA(D8/0x48128) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#CE14:
Area 14 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A14DRA(D8/0x48122) = "0" and SDRPC1(D2/0x39FFC0) = "0"
#RAS3:
Area 14 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A14DRA(D8/0x48122) = "1" and SDRPC1(D2/0x39FFC0) = "0"
#SDCE1:
SDRAM chip enable 1 when SDRPC1(D2/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
–
#CE7:
Area 7 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "0" and SDRPC0(D3/0x39FFC0) = "0" (default)
#RAS0:
Area 7 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "00",
A7DRA(D7/0x48128) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#CE13:
Area 13 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01" or "1x",
A13DRA(D7/0x48122) = "0" and SDRPC0(D3/0x39FFC0) = "0"
#RAS2:
Area 13 DRAM row strobe when CEFUNC[1:0](D[A:9]/0x48130) = "01" or
"1x", A13DRA(D7/0x48122) = "1" and SDRPC0(D3/0x39FFC0) = "0"
#SDCE0:
SDRAM chip enable 0 when SDRPC0(D3/0x39FFC0) = "1" and
SDRENA(D7/0x39FFC1) = "1"
–
Area 6 chip enable
* When CEFUNC[1:0] = "1x", this pin outputs #CE7+#CE8 signal.
–
#CE5:
Area 5 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE15:
Area 15 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE15+#CE16 signal.
–
#CE4:
Area 4 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "00" (default)
#CE11:
Area 11 chip enable when CEFUNC[1:0](D[A:9]/0x48130) = "01"
* When CEFUNC[1:0] = "1x", this pin outputs #CE11+#CE12 signal.
–
Area 3 chip enable
–
Read signal
–
Read signal for internal ROM emulation memory
–
#WRL:
Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#WR:
Write signal when SBUSST(D3/0x4812E) = "1"
#WE:
DRAM write signal
–
#WRH:
Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#BSH:
Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"
EPSON
I OUTLINE: LIST OF PINS
Function
A-1
B-I
Pin
B-I-3-1
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