Dram (70Ns - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
A.1 DRAM (70ns)
DRAM interface setup examples – 70ns
Operating RAS precharge
frequency
20MHz
25MHz
33MHz
DRAM interface timing – 70ns
DRAM interface
Parameter
<Common parameters>
Random read/random write cycle time
#RAS precharge time
#RAS pulse width
#CAS pulse width
Row address setup time
Row address hold time
Column address setup time
#RAS #CAS delay time
#RAS column address delay time
<Read-cycle parameters>
#RAS access time
#CAS access time
Address access time
#OE access time
Output buffer turn-off time
<Write-cycle parameters>
Data input hold time
<Fast-page mode>
Fast-page mode cycle time
Fast-page mode #CAS precharge time
Access time after #CAS precharge
<Refresh cycle>
#CAS setup time
#CAS hold time
#RAS precharge #CAS hold time
#RAS pulse width (only in refresh cycle)
A-114
RAS cycle
cycle
2 1
2 1
2 2
Unit: ns
Symbol Min.
t
130
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
RCD
t
RAD
t
RAC
t
CAC
t
AA
t
OAC
t
OFF
t
DH
t
PC
t
CP
t
ACP
t
CSR
t
CHR
t
PPC
t
RAS
CAS cycle
2
2
3
33MHz
Max. Cycle Time
– 7 210
50 – 2 60
70 10000 5 150
20 10000 2.5 75
0 – 0.5 15
10 – 1.5 45
0 – 0.5 15
20 – 2.0 60
15 – 1.5 45
– 70 4.5 135
– 20 2.5 75
– 35 3.0 90
– 20 4.5 135
0 20 2 60
15 – 2.5 75
45 – 3.0 90
10 – 0.5 15
– 40 3.0 90
10 – 1.0 30
10 – 2.5 75
10 – 1.0 30
70 10000 3.0 90
EPSON
Refresh RAS pulse
Refresh RPC delay
width
2
2
3
25MHz
Cycle Time Cycle
5 200 5
2 80 2
3 120 3
1.5 60 1.5
0.5 20 0.5
0.5 20 0.5
0.5 20 0.5
1.0 40 1.0
0.5 20 0.5
2.5 100 2.5
1.5 60 1.5
2.0 80 2.0
2.5 100 2.5
2 80 2
1.5 60 1.5
2.0 80 2.0
0.5 20 0.5
2.0 80 2.0
1.0 40 1.0
1.5 60 1.5
1.0 40 1.0
2.0 80 2.0
S1C33L03 PRODUCT PART
1
1
1
20MHz
Time
250
100
150
75
25
25
25
50
25
125
75
100
125
100
75
100
25
100
50
75
50
100