Dram (60Ns - Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual

Cmos 32-bit single chip microcomputer
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A.2 DRAM (60ns)
DRAM interface setup examples – 60ns
Operating
RAS precharge
frequency
cycle
20MHz
25MHz
33MHz
DRAM interface timing – 60ns
DRAM interface
Parameter
<Common parameters>
Random read/random write cycle time
#RAS precharge time
#RAS pulse width
#CAS pulse width
Row address setup time
Row address hold time
Column address setup time
#RAS #CAS delay time
#RAS column address delay time
<Read-cycle parameters>
#RAS access time
#CAS access time
Address access time
#OE access time
Output buffer turn-off time
<Write-cycle parameters>
Data input hold time
<Fast-page mode>
Fast-page mode cycle time
Fast-page mode #CAS precharge time
Access time after #CAS precharge
<Refresh cycle>
#CAS setup time
#CAS hold time
#RAS precharge #CAS hold time
#RAS pulse width (only in refresh cycle)
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
RAS cycle
1
1
2
1
2
2
Unit: ns
Symbol
Min.
t
110
RC
t
40
RP
t
60
RAS
t
15
CAS
t
0
ASR
t
10
RAH
t
0
ASC
t
20
RCD
t
15
RAD
t
RAC
t
CAC
t
AA
t
OAC
t
0
OFF
t
10
DH
t
40
PC
t
10
CP
t
ACP
t
10
CSR
t
10
CHR
t
10
PPC
t
60
RAS
EPSON
Refresh RAS pulse
CAS cycle
width
2
2
2
33MHz
Max.
Cycle
Time
Cycle
6
180
2
60
10000
4
120
10000
1.5
45
1.5
0.5
15
0.5
1.5
45
0.5
0.5
15
0.5
2.0
60
1.0
1.5
45
0.5
60
3.5
105
2.5
15
1.5
45
1.5
30
2.0
60
2.0
15
3.5
105
2.5
15
2
60
1.5
45
1.5
2.0
60
2.0
0.5
15
0.5
35
2.0
60
2.0
1.0
30
1.0
2.5
75
1.5
1.0
30
1.0
10000
3.0
90
2.0
Refresh RPC delay
2
1
2
1
3
1
25MHz
20MHz
Time
Cycle
Time
5
200
4
200
2
80
1
50
3
120
3
150
60
1.5
75
20
0.5
25
20
0.5
25
20
0.5
25
40
1.0
50
20
0.5
25
100
2.5
125
60
1.5
75
80
2.0
100
100
2.5
125
2
80
1
50
60
1.5
75
80
2.0
100
20
0.5
25
80
2.0
100
40
1.0
50
60
1.5
75
40
1.0
50
80
2.0
100
A-117
A-1
A-ap

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