Figure 9-4 Clock Synchronization - Epson ARM720T Core Cpu Manual

9: Debugging Your System
9.3.5 Clocks
The system and test clocks must be synchronized externally to the processor. The ARM
Multi-ICE debug agent directly supports one or more cores within an ASIC design.
Synchronizing off-chip debug clocking with the ARM720T processor requires a three-stage
synchronizer. The off-chip device (for example, Multi-ICE) issues a TCK signal and waits for
the RTCK (Returned TCK) signal to come back. Synchronization is maintained because the
off-chip device does not progress to the next TCK until after RTCK is received.
Figure 9-4 shows this synchronization.
nTRST
TDO
RTCK
TCK
TMS
TDI
Multi_ICE interface pads
All the D-types shown in Figure 9-4 are reset by DBGnTRST.
Note:
9-8
TCK synchronizer
D Q D
HCLK

Figure 9-4 Clock synchronization

EPSON
Reset circuit
Q D Q
HCLK
ARM720T CORE CPU MANUAL
DBGnTRST
DBGTDO
DBGTCKEN
DBGTMS
EN
D Q
DBGTDI
EN
D Q
HCLK
Input sample
and hold
HCLK