Programming Breakpoints - Epson ARM720T Core Cpu Manual

9: Debugging Your System
DBGEXT[1:0]
CHAIN
RANGE
ENABLE
For each of the bits [7:0] in the control value register, there is a corresponding bit in the control
mask register. This removes the dependency on particular signals.
9.21

Programming breakpoints

Breakpoints are classified as hardware breakpoints or software breakpoints:
Hardware breakpoints
•
code, even in code that is in ROM or code that is self-modifying. See
breakpoints
Software breakpoints
•
address. One EmbeddedICE-RT watchpoint can therefore be used to support any
number of software breakpoints. See
Software breakpoints can usually be set only in RAM because a special bit pattern
chosen to cause a software breakpoint has to replace the instruction.
9.21.1 Hardware breakpoints
To make a watchpoint unit cause hardware breakpoints (on instruction fetches):
1 Program its address value register with the address of the instruction to be
breakpointed.
2 Program the breakpoint bits for each state as follows:
For an ARM state breakpoint
For a Thumb state breakpoint
In either case, clear the remaining bits.
9-36
Is an external input to EmbeddedICE-RT logic that enables the
watchpoint to be dependent on some external condition.
The DBGEXT input for Watchpoint 0 is labeled DBGEXT[0].
The DBGEXT input for Watchpoint 1 is labeled DBGEXT[1].
Can be connected to the chain output of another watchpoint in
order to implement, for example, debugger requests of the form
breakpoint on address YYY only when in process XXX
In the ARM720T processor EmbeddedICE-RT macrocell, the
CHAINOUT output of Watchpoint 1 is connected to the CHAIN
input of Watchpoint 0.
The CHAINOUT output is derived from a register. The
address/control field comparator drives the write enable for the
register. The input to the register is the value of the data field
comparator.
The CHAINOUT register is cleared when the control value register
is written, or when DBGnTRST is LOW.
In the ARM720T processor EmbeddedICE-RT logic, the DBGRNG
output of Watchpoint 1 is connected to the RANGE input of
Watchpoint 0. Connection enables the two watchpoints to be
coupled for detecting conditions that occur simultaneously, for
example in range checking.
When a watchpoint match occurs, the internal DBGBREAK signal
is asserted only when the ENABLE bit is set. This bit exists only in
the value register. It cannot be masked.
typically monitor the address value and can be set in any
for more details.
monitor a particular bit pattern being fetched from any
Set bits [1:0] of the address mask register.
Set bit 0 of the address mask register.
Software breakpoints
EPSON
.
Hardware
for more details.
ARM720T CORE CPU MANUAL