Figure 9-12 Embeddedice-Rt Block Diagram - Epson ARM720T Core Cpu Manual

9: Debugging Your System
Scan chain
register
read/write
4
Address
0
31
Data
0
DBGTDI DBGTDO
The data to be written is shifted into the 32-bit data field, the address of the register is shifted
into the 5-bit address field, and the read/write bit is set.
The data to be written is scanned into the 32-bit data field, the address of the register is
scanned into the 5-bit address field, and the read/write bit is set.
A register is read by shifting its address into the address field, and by shifting a 0 into the
read/write bit. The 32-bit data field is ignored.
The register addresses are shown in Table 9-1 on page 9-12.
A read or write takes place when the TAP controller enters the UPDATE-DR state.
Note:
9-34
Address decoder
32
Value
HADDR[31:0]
DATA[31:0]
Control
Watchpoint registers and comparators

Figure 9-12 EmbeddedICE-RT block diagram

EPSON
Mask Comparator
ARM720T CORE CPU MANUAL
Update
+
Breakpoint
condition