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A: Signal Descriptions
Output name
ETMTBIT
ETMBIGEND
ETMEN
ETMHIVECS
ETMSIZE[1:0]
ETMRDATA[31:0]
ETMWDATA[31:0]
ETMINSTRVALID
ETMnRW
ETMCLKEN
A-6
Table A-5 ETM interface signal descriptions (continued)
Type
Description
Output
Thumb state.
This signal, when HIGH, indicates that the processor is executing the
THUMB instruction set. When LOW, the processor is executing the
ARM instruction set.
Output
Big-endian format.
When this signal is HIGH, the processor treats bytes in memory as
being in big-endian format. When it is LOW, memory is treated as
little-endian.
Input
The ETM7 enable signal.
Output
When LOW, this signal indicates that the exception vectors start at
address 0x00000000. When HIGH, the exception vectors start at
address 0xFFFF0000.
Output
The memory access size bus driven by the ARM720T processor.
Output
The processor read data bus.
Output
The processor write data bus.
Output
The instruction valid signal driven by the ARM720T processor. When
HIGH, it indicates that the instruction in the Execute stage is valid and
has not been flushed.
Output
Not read/write. When HIGH, indicates a processor write cycle. When
LOW, indicates a processor read cycle.
Output
This signal is used to indicate to the ETM that the core is in a wait state.
It is not a true clock enable for the ETM.
EPSON
ARM720T CORE CPU MANUAL
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