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7: Memory Management Unit
7.3.4
Section descriptor
A section descriptor provides the base address of a 1MB block of memory. Figure 7-5 shows the
format of a section descriptor.
31
Section base address
Section descriptor bit assignments are described in Table 7-4.
Bits
31:20
19:12
11:10
9
8:5
4
3:2
1:0
7.3.5
Coarse page table descriptor
A coarse page table descriptor provides the base address of a page table that contains level two
descriptors for either large page or small page accesses. Coarse page tables have 256 entries,
splitting the 1MB that the table describes into 4KB blocks. Figure 7-6 shows the format of a
coarse page table descriptor.
31
If a coarse page table descriptor is returned from the level one fetch, a level two
Note:
fetch is initiated.
7-8
20 19
Figure 7-5 Section descriptor
Table 7-4 Section descriptor bits
Description
Form the corresponding bits of the physical address for a section
Always written as 0
(AP) Specify the access permissions for this section
Always written as 0
Specify one of the 16 possible domains (held in the Domain
Access Control Register) that contain the primary access
controls
Should be written as 1, for backward compatibility
These bits, C and B, indicate whether the area of memory
mapped by this page is treated as cachable or noncachable, and
bufferable or nonbufferable. (The system is always
write-through.)
These bits must be b10 to indicate a section descriptor
Coarse page table base address
Figure 7-6 Coarse page table descriptor
12 11 10 9 8
SBZ
AP
Domain
SBZ
10 9 8
Domain
SBZ
EPSON
5 4 3 2 1 0
1 C B 1 0
5 4 3 2 1 0
1
SBZ
0 1
ARM720T CORE CPU MANUAL
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