The Debug Communications Channel; Figure 9-6 Domain Access Control Register - Epson ARM720T Core Cpu Manual

9: Debugging Your System
9.10

The debug communications channel

The ARM720T EmbeddedICE-RT macrocell contains a
for passing information between the target and the host debugger. This is implemented as
coprocessor 14.
The DCC comprises two registers, as follows:
DCC Control Register
DCC Data Register
These registers occupy fixed locations in the EmbeddedICE-RT memory map, as shown in
Table 9-1 on page 9-12. They are accessed from the processor using MCR and MRC
instructions to coprocessor 14.
The registers are accessed as follows:
By the debugger
By the processor
9.10.1 Domain Access Control Register
The Domain Access Control Register is read-only and enables synchronized handshaking
between the processor and the debugger. The register format is shown in Figure 9-6.
31 28 27
EmbeddedICE-RT version number
9-14
A 32-bit register, used for synchronized handshaking between the
processor and the asynchronous debugger. For more details, see
Domain Access Control Register
A 32-bit register, used for data transfers between the debugger and
the processor. For more details, see
DCC
on page 9-16.
Through scan chain 2 in the usual way.
Through coprocessor register transfer instructions.

Figure 9-6 Domain Access Control Register

EPSON
Debug Communication Channel
.
Communications through the
SB0
ARM720T CORE CPU MANUAL
(DCC)
2 1 0
W R