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2
Programmer's Model
This chapter describes the programmer's model for the ARM720T processor. It contains the
following sections:
2.1
Processor operating states ......................................................................... 2-1
2.2
Memory formats ......................................................................................... 2-2
2.3
Instruction length ...................................................................................... 2-3
2.4
Data types................................................................................................... 2-3
2.5
Operating modes ........................................................................................ 2-4
2.6
Registers ..................................................................................................... 2-4
2.7
Program status registers ........................................................................... 2-8
2.8
Exceptions................................................................................................. 2-10
2.9
Relocation of low virtual addresses by the FCSE PID ........................... 2-15
2.10
Reset.......................................................................................................... 2-16
2.11
Implementation-defined behavior of instructions .................................. 2-17
2.1
Processor operating states
From the point of view of the programmer, the ARM720T processor can be in one of two states:
ARM state
Thumb state
2.1.1
Switching between processor states
Transition between processor states does not affect the processor mode or the contents of the
registers.
Entering Thumb state
Entry into Thumb state can be achieved by executing a BX instruction with the state bit (bit
0) set in the operand register.
Transition to Thumb state also occurs automatically on return from an exception, for example,
Interrupt ReQuest
(IRQ),
Interrupt
(SWI) if the exception was entered with the processor in Thumb state.
Entering ARM state
Entry into ARM state happens:
•
On execution of the BX instruction with the state bit clear in the operand register.
•
On the processor taking an exception, for example, IRQ, FIQ, RESET, UNDEF,
ABORT, and SWI. In this case, the PC is placed in the link register of the exception
mode, and execution starts at the vector address of the exception.
ARM720T CORE CPU MANUAL
This executes 32-bit, word-aligned ARM instructions.
This operates with 16-bit, halfword-aligned Thumb instructions. In
this state, the PC uses bit 1 to select between alternate halfwords.
Fast Interrupt reQuest
EPSON
(FIQ), UNDEF, ABORT, and
2: Programmer's Model
SoftWare
2-1
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