Epson ARM720T Core Cpu Manual page 9

Figure 9-4 Clock synchronization ................................................................................. 9-8
Figure 9-5 The ARM720T core, TAP controller, and EmbeddedICE-RT macrocell ... 9-10
Figure 9-6 Domain Access Control Register .............................................................. 9-14
Figure 9-7 ARM720T processor scan chain arrangements........................................ 9-17
Figure 9-8 Test access port controller state transitions.............................................. 9-19
Figure 9-9 ID code register format.............................................................................. 9-22
Figure 9-10 Scan timing ............................................................................................... 9-25
Figure 9-11 Debug exit sequence ................................................................................ 9-29
Figure 9-12 EmbeddedICE-RT block diagram ............................................................. 9-34
Figure 9-13 Watchpoint control value, and mask format .............................................. 9-35
Figure 9-14 Debug abort status register....................................................................... 9-38
Figure 9-15 Debug control register format.................................................................... 9-39
Figure 9-16 Debug status register format..................................................................... 9-41
Figure 9-17 Debug control and status register structure .............................................. 9-42
Figure 11-1 CP15 MRC and MCR bit pattern............................................................... 11-1
Figure 11-2 Rd format, CAM read ................................................................................ 11-4
Figure 11-3 Rd format, CAM write................................................................................ 11-4
Figure 11-4 Rd format, RAM read ................................................................................ 11-5
Figure 11-5 Rd format, RAM write................................................................................ 11-5
Figure 11-6 Rd format, CAM match RAM read ............................................................ 11-5
Figure 11-7 Data format, CAM read ............................................................................. 11-5
Figure 11-8 Data format, RAM read ............................................................................. 11-5
Figure 11-9 Data format, CAM match RAM read ......................................................... 11-6
Figure 11-10 Rd format, write cache victim and lockdown base .................................... 11-6
Figure 11-11 Rd format, write cache victim .................................................................... 11-6
Figure 11-12 Rd format, CAM write and data format, CAM read ................................. 11-10
Figure 11-13 Rd format, RAM1 write............................................................................ 11-10
Figure 11-14 Data format, RAM1 read ......................................................................... 11-11
Figure 11-15 Rd format, RAM2 write and data format, RAM2 read ............................. 11-11
Figure 11-16 Rd format, write TLB lockdown ............................................................... 11-12
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