Table of Contents
Advertisement
Bits 12:10
Using a read-write-modify sequence when modifying this register provides the
Note:
greatest future compatibility.
V Bit 13
Bits 31:14
Enabling the MMU
You must take care if the translated address differs from the untranslated address, because
the instructions following the enabling of the MMU are fetched using no address translation.
Enabling the MMU can be considered as a branch with delayed execution.
A similar situation occurs when the MMU is disabled. The correct code sequence for enabling
and disabling the MMU is given
Note:
•
When the MMU is disabled the Cache is disabled.
•
If the cache and write buffer are enabled when the MMU is not enabled, the results
are Unpredictable.
3.3.3
Translation Table Base Register
Reading from CP15 Register 2 returns the pointer to the currently active first-level
translation table in bits [31:14] and an Unpredictable value in bits [13:0]. The CRm and
opcode_2 fields Should Be Zero when reading CP15 Register 2.
Writing to CP15 Register 2 updates the pointer to the currently active first-level translation
table from the value in bits [31:14] of the written value. Bits [13:0] Should Be Zero. The CRm
and opcode_2 fields Should Be Zero when writing CP15 Register 2. Translation Table Base
Register format is shown in Figure 3-6.
31
ARM720T CORE CPU MANUAL
When read, this returns an Unpredictable value. When written, it
Should Be Zero, or a value read from these bits on the same
processor.
Location of exception vectors:
0 = low addresses
1 = high addresses.
The value of the V bit reflects the state of the VINITHI external
input, sampled while HRESETn is LOW.
When read, this returns an Unpredictable value. When written, it
Should Be Zero, or a value read from these bits on the same
processor.
Interaction of the MMU and cache
Translation base table
Figure 3-6 Translation Table Base Register format
EPSON
on page 7-21.
14 13
UNP/SBZ
3: Configuration
00
3-5
Advertisement
Table of Contents
