Figure 1-2 Arm720T Processor Functional Signals - Epson ARM720T Core Cpu Manual

The functional signals on the ARM720T processor are shown in Figure 1-2.
A MBA
interf ace
Coprocessor
interf ace
Debug
interf ace
Miscellaneous
signals
A TPG
Signals
1.1.1 EmbeddedICE-RT logic
The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM720T core.
It enables you to program the conditions under which a breakpoint or watchpoint can occur.
The EmbeddedICE-RT logic is an enhanced implementation of EmbeddedICE, and enables
you to perform debugging in monitor mode. In monitor mode, the core takes an exception on a
breakpoint or watchpoint, rather than entering debug state as it does in halt mode.
If the core does not enter debug state when it encounters a watchpoint or breakpoint, it can
continue to service hardware interrupt requests as normal. Debugging in monitor mode is
useful if the core forms part of the feedback loop of a mechanical system, where stopping the
core can potentially lead to system failure.
The EmbeddedICE-RT logic contains a
used to pass information between the target and the host debugger. The EmbeddedICE-RT
logic is controlled through the
ARM720T CORE CPU MANUAL
HADDR[31:0]
HTRANS[1:0]
HBURST[2:0]
HWRITE
HSIZE[2:0]
HPROT[3:0]
HGRANT
HREADY
HRESP[1:0]
HWDATA[31:0]
HRDATA[31:0]
HBUSREQ
HLOCK
HCLKEN
EXTCPCLKEN
EXTCPDIN[31:0]
EXTCPDOUT[31:0]
EXTCPA
EXTCPB
CPnCPI
A RM720T processor
CPnOPC
CPTBIT
CPnTRANS
CPnM REQ
EXTCPDBE
COM M RX
COM M TX
DBGACK
DBGEN
DBGRQ
DBGEXT[1:0]
DBGRNG[1:0]
DBGBREAK
BIGENDOUT
nFIQ
nIRQ
V INITHI
HRESETn
HCLK
TESTENABLE
SCANENABLE

Figure 1-2 ARM720T processor functional signals

Debug Communications Channel
Joint Test Action Group
EPSON
DBGIR[3:0]
DBGSREG[3:0]
DBGSDIN
DBGSDOUT
DBGTAPSM [3:0]
DBGCAPTURE
DBGSHIFT
DBGUPDATE
DBGINTEST
DBGEXTEST
DBGnTDOEN
DBGnTRST
DBGTCKEN
DBGTDI
DBGTDO
DBGTM S
ETM EN
ETM BIGEND
ETM HIV ECS
ETM nM REQ
ETM nOPC
ETM SEQ
ETM nEXEC
ETM INSTRV ALID
ETM nCPI
ETM ADDR[31:0]
ETM nRW
ETM CLKEN
ETM SIZE[1:0]
ETM DBGACK
ETM RDATA[31:0]
ETM WDATA[31:0]
ETM ABORT
ETM CPA
ETM CPB
ETM TBIT
ETM PROCID[31:0]
ETM PROCIDWR
SCANIN0 - SCANIN6
SCANOUT0 - SCANOUT6
(DCC). The DCC is
(JTAG) test access port.
1: Introduction
JTA G
interf ace
ETM interf ace
A TPG
Signals
1-3