Figure 1-3 Arm Instruction Set Formats - Epson ARM720T Core Cpu Manual

1.3.2 ARM instruction set
This section gives an overview of the ARM instructions available. For full details of these
ARM Architecture Reference Manual
instructions, see the
The ARM instruction set formats are shown in Figure 1-3.
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Data processing
immediate
Data processing
immediate shift
Data processing register
shift
Multiply
Multiply long
Move from status register
Move immediate to status
register
Move register to status
register
Branch/exchange
instruction set
Load/store immediate
offset
Load/store register offset
Load/store halfword/
signed byte
Load/store halfword/
signed byte
Swap/swap byte
Load/store multiple
Coprocessor data
processing
Coprocessor register
transfers
Coprocessor load and
store
Branch and branch with
link
Software interrupt
Undefined
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Some instruction codes are not defined but do not cause the Undefined instruction
Note:
trap to be taken, for example, a multiply instruction with bit 6 set. You must not
use these instructions, because their action might change in future ARM
implementations.
ARM720T CORE CPU MANUAL
cond 0 0 1 op
cond 0 0 0 opcode
cond 0 0 0 opcode
cond 0 0 0 0 0 0 A S
cond 0 0 0 0 1 U A
cond 0 0 0 1 0 R 0 0
cond 0 0 1 1 0 R 1 0
cond 0 0 0 1 0 R 1 0
cond 0 0 0 1 0 0 1 0
cond 0 1 0 P U B W L
cond 0 1 1 P U B W L
cond 0 0 0 P U 1 W
cond 0 0 0 P U 0 W
cond 0 0 0 1 0 B 0 0
cond 1 0 0 P U S W L
cond 1 1 1 0 op1
cond 1 1 1 0 op1
cond 1 1 0 P U N W L
cond 1 0 1 L
cond 1 1 1 1
cond 0 1 1 x x x x x x x x x x x x x x x x x x x x

Figure 1-3 ARM instruction set formats

.
S Rn Rd rotate
S Rn Rd shift immediate shift 0
S Rn Rd
Rd Rn
S RdHi RdLo
SBO Rd
Mask SBO rotate
Mask SBO
SBO SBO
Rn Rd
Rn Rd shift immediate shift 0
L Rn Rd High offset 1 S H 1
L Rn Rd
Rn Rd
Rn
CRn CRd cp_num
L CRn Rd cp_num
Rn CRd cp_num
24_bit_offset
swi_number
EPSON
1: Introduction
immediate
Rm
Rs 0 shift 1 Rm
Rs 1 0 0 1 Rm
Rn 1 0 0 1 Rm
SBZ
immediate
SBZ 0 Rm
SBO 0 0 0 1 Rm
immediate
Rm
Low offset
SBZ 1 S H 1 Rm
SBZ 1 0 0 1 Rm
Register list
op2 0 CRm
op2 1 CRm
8_bit_offset
1 x x x x
1-7