Table 1-3 Addressing Mode 2 - Epson ARM720T Core Cpu Manual

1: Introduction
Operation
Coprocessors Data operations
Move to ARM reg from coproc
Move to coproc from ARM reg
Load
Store
Software
Interrupt
Addressing mode 2, <a_mode2>, is shown in Table 1-3.
Operation
Immediate offset
Register offset
Scaled register offset
Pre-indexed immediate offset
Pre-indexed register offset
Pre-indexed scaled register offset
Post-indexed immediate offset
Post-indexed register offset
Post-indexed scaled register offset
1-10
Table 1-2 ARM instruction summary (continued)

Table 1-3 Addressing mode 2

Assembler
CDP{cond} p<cpnum>, <op1>, <CRd>, <CRn>,
<CRm>, <op2>
MRC{cond} p<cpnum>, <op1>, <Rd>, <CRn>,
<CRm>, <op2>
MCR{cond} p<cpnum>, <op1>, <Rd>, <CRn>,
<CRm>, <op2>
LDC{cond} p<cpnum>, <CRd>, <a_mode5>
STC{cond} p<cpnum>, <CRd>, <a_mode5>
SWI <24bit_Imm>
Assembler
[<Rn>, #+/-<12bit_Offset>]
[<Rn>, +/-<Rm>]
[<Rn>, +/-<Rm>, LSL #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, LSR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, ASR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, ROR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, RRX]
[<Rn>, #+/-<12bit_Offset>]!
[<Rn>, +/-<Rm>]!
[<Rn>, +/-<Rm>, LSL #<5bit_shift_imm>]!
[<Rn>, +/-<Rm>, LSR #<5bit_shift_imm>]!
[<Rn>, +/-<Rm>, ASR #<5bit_shift_imm>]!
[<Rn>, +/-<Rm>, ROR #<5bit_shift_imm>]!
[<Rn>, +/-<Rm>, RRX]!
[<Rn>], #+/-<12bit_Offset>
[<Rn>], +/-<Rm>
[<Rn>], +/-<Rm>, LSL #<5bit_shift_imm>
[<Rn>], +/-<Rm>, LSR #<5bit_shift_imm>
[<Rn>], +/-<Rm>, ASR #<5bit_shift_imm>
[<Rn>], +/-<Rm>, ROR #<5bit_shift_imm>
[<Rn>, +/-<Rm>, RRX]
EPSON ARM720T CORE CPU MANUAL