Epson ARM720T Core Cpu Manual page 36

1: Introduction
Operation
Shift/Rotate
Branch Conditional
Unconditional
Load With immediate offset
1-16
Table 1-12 Thumb instruction summary (continued)
Logical shift left
Logical shift right
Arithmetic shift right
Rotate right
if Z set
if Z clear
if C set
if C clear
if N set
if N clear
if V set
if V clear
if C set, and Z clear
if C clear, and Z set
if N set, and V set, or if N
clear, and V clear
if N set, and V clear, or if
N clear, and V set
if Z clear, and N, or V set,
or if Z clear, and N, or V
clear
if Z set, or N set, and V
clear, or N clear, and V
set
Long branch with link
Optional state change
to address held in Lo reg
to address held in Hi reg
word
halfword
byte
Assembler
LSL <Rd>, <Rs>, #<5bit_shift_imm> LSL
<Rd>, <Rs>
LSR <Rd>, <Rs>, #<5bit_shift_imm> LSR
<Rd>, <Rs>
ASR <Rd>, <Rs>, #<5bit_shift_imm> ASR
<Rd>, <Rs>
ROR <Rd>, <Rs>
BEQ <label>
BNE <label>
BCS <label>
BCC <label>
BMI <label>
BPL <label>
BVS <label>
BVC <label>
BHI <label>
BLS <label>
BGE <label>
BLT <label>
BGT <label>
BLE <label>
B <label>
BL <label>
BX <Rs>
BX <Hs>
LDR <Rd>, [<Rb>, #<7bit_offset>]
LDRH <Rd>, [<Rb>, #<6bit_offset>]
LDRB <Rd>, [<Rb>, #<5bit_offset>]
EPSON ARM720T CORE CPU MANUAL