Slave Transfer Response Signals - Epson ARM720T Core Cpu Manual

6.5

Slave transfer response signals

After a master has started a transfer, the slave determines how the transfer progresses. No
provision is made in the AHB specification for a bus master to cancel a transfer after it has
begun.
Whenever a slave is accessed it must provide a response using the following signals:
HRESP[1:0]
HREADY
The slave can complete the transfer in a number of ways. It can:
• complete the transfer immediately
• insert one or more wait states to enable time to complete the transfer
• signal an error to indicate that the transfer has failed
• delay the completion of the transfer, but enable the master and slave to back off the
bus, leaving it available for other transfers.
6.5.1 HREADY
The HREADY signal is used to extend the data portion of an AHB transfer, as follows:
HREADY LOW
HREADY HIGH
Every slave must have a predetermined maximum number of wait states that it inserts before
it backs off the bus, in order to enable the calculation of the latency of accessing the bus. To
prevent any single access locking the bus for a large number of clock cycles, it is recommended
that slaves do not insert more than 16 wait states.
ARM720T CORE CPU MANUAL
Indicates the status of the transfer.
Used to extend the transfer. This signal works in combination with
HRESP[1:0].
Indicates that the transfer data is to be extended. It causes wait
states to be inserted into the transfer and enables extra time for
the slave to provide or sample data.
Indicates that the transfer can complete.
EPSON
6: The Bus Interface
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