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A.6
ATPG test signals
ATPG test signals used by the ARM720T processor are shown in Table A-6.
Name
TESTENABLE
SCANENABLE
SCANIN0-SCANIN6
SCANOUT0-SCANOUT6
HCLK
HCLKEN
DBGTCKEN
HRESETn
DBGnTRST
A.7
Miscellaneous signals
Miscellaneous signals used by the ARM720T processor are shown in Table A-7.
Name
Type
BIGENDOUT
Output
nFIQ
Input
nIRQ
Input
VINITHI
Input
ARM720T CORE CPU MANUAL
Table A-6 ATPG test signal descriptions
Type
Description
Input
This signal ensures the clocks are free-running during scan
test. TESTENABLE must be:
•
•
Input
This signal enables serial shifting of vectors through the scan
chains. You must control this signal using the I/O pins. It must
be tied LOW during functional mode.
Inputs
Processor core scan chain inputs.
Outputs
Processor core scan chain outputs.
Input
System clock. All signals are related to the rising edge of
HCLK.
Input
Synchronous enable for AHB transfers. When HIGH,
indicates that the next rising edge of HCLK is also a rising
edge for the AHB system that the ARM720T processor is
embedded in. Must be tied HIGH in systems where the AMBA
bus and the core are intended to be the same frequency.
Input
Synchronous enable for debug logic. Must be tied HIGH
during scan test.
Input
This is the active LOW reset signal for the system and bus.
Input
This is the active LOW reset signal for the internal state. This
signal is a level-sensitive asynchronous reset input.
Table A-7 Miscellaneous signal descriptions
Description
Big-endian format.
When this signal is HIGH, the processor treats bytes in memory as being in
big-endian format. When it is LOW, memory is treated as little-endian.
ARM fast interrupt request signal.
ARM interrupt request signal.
Determines the state of the V bit in CP15 register c1 at reset. When HIGH, the
V bit is set coming out of rest. When LOW, the V bit is clear coming out of
reset.
EPSON
tied HIGH throughout the duration of scan testing
tied LOW during functional mode.
A: Signal Descriptions
A-7
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