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2: Programmer's Model
2.10
Reset
When the HRESETn signal goes LOW, the ARM720T processor:
1
Abandons the executing instruction.
2
Flushes the cache and
3
Disables the
4
Resets the FCSE PID.
5
Continues to fetch instructions from incrementing word addresses.
When HRESETn is LOW, the processor samples the VINITHI external input and stores the
result in the V bit in CP15 register 1.
When HRESETn goes HIGH again, the ARM720T processor:
1
Overwrites r14_svc and SPSR_svc by copying the current values of the PC and
CPSR into them. The value of the saved PC and SPSR is not defined.
2
Forces M[4:0] to b10011 (Supervisor mode), sets the I and F bits in the CPSR, and
clears the CPSR T bit.
3
Forces the PC to fetch the next instruction from the reset exception vector.
Exception vectors are located at either high or low addresses depending on the state
of the V bit in CP15 register 1 (LOW = low addresses, HIGH = high addresses).
4
Resumes execution in ARM state.
2-16
Translation Lookaside Buffer
Write Buffer
(WB), cache, and MMU.
EPSON
(TLB).
ARM720T CORE CPU MANUAL
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