Table 1-4 Addressing Mode 2 (Privileged); Table 1-6 Addressing Mode 4 (Load) - Epson ARM720T Core Cpu Manual

Addressing mode 2 (privileged), <a_mode2P>, is shown in Table 1-4.
Operation
Immediate offset
Register offset
Scaled register offset
Post-indexed immediate offset
Post-indexed register offset
Post-indexed scaled register offset
Addressing mode 3 (signed byte, and halfword data transfer), <a_mode3>, is shown in
Table 1-5.
Addressing mode 4 (load), <a_mode4L>, is shown in Table 1-6.
ARM720T CORE CPU MANUAL

Table 1-4 Addressing mode 2 (privileged)

Table 1-5 Addressing mode 3
Operation
Immediate offset
Pre-indexed
Post-indexed
Register
Pre-indexed
Post-indexed

Table 1-6 Addressing mode 4 (load)

Addressing mode
IA Increment after
IB Increment before
DA Decrement after
DB Decrement before
Assembler
[<Rn>, #+/-<12bit_Offset>]
[<Rn>, +/-<Rm>]
[<Rn>, +/-<Rm>, LSL #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, LSR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, ASR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, ROR #<5bit_shift_imm>]
[<Rn>, +/-<Rm>, RRX]
[<Rn>], #+/-<12bit_Offset>
[<Rn>], +/-<Rm>
[<Rn>], +/-<Rm>, LSL #<5bit_shift_imm>
[<Rn>], +/-<Rm>, LSR #<5bit_shift_imm>
[<Rn>], +/-<Rm>, ASR #<5bit_shift_imm>
[<Rn>], +/-<Rm>, ROR #<5bit_shift_imm>
[<Rn>, +/-<Rm>, RRX]
Assembler
[<Rn>, #+/-<8bit_Offset>]
[<Rn>, #+/-<8bit_Offset>]!
[<Rn>], #+/-<8bit_Offset>
[<Rn>, +/-<Rm>]
[<Rn>, +/-<Rm>]!
[<Rn>], +/-<Rm>
Stack type
FD Full descending
ED Empty descending
FA Full ascending
EA Empty ascending
EPSON
1: Introduction
1-11