Watchpoint Unit Registers - Epson ARM720T Core Cpu Manual

9.19.2 Interrupts
When the ARM720T processor enters debug state, interrupts are automatically disabled.
If an interrupt is pending during the instruction prior to entering debug state, the ARM720T
processor enters debug state in the mode of the interrupt. On entry to debug state, the
debugger cannot assume that the ARM720T processor is in the mode expected by the program
of the user. The ARM720T core must check the PC, the CPSR, and the SPSR to determine
accurately the reason for the exception.
Debug, therefore, takes higher priority than the interrupt, but the ARM720T processor does
remember that an interrupt has occurred.
9.19.3 Data Aborts
When a Data Abort occurs on a watchpointed access, the ARM720T processor enters debug
state in abort mode. The watchpoint, therefore, has higher priority than the abort, but the
ARM720T processor remembers that the abort happened.
9.20

Watchpoint unit registers

There are two watchpoint units, known as
either to be a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction
fetches). You can make watchpoints and breakpoints data-dependent.
Each watchpoint unit contains three pairs of registers:
• address value and address mask
• data value and data mask
• control value and control mask.
Each register is independently programmable and has a unique address. The function and
mapping of the watchpoint unit register is shown in Table 9-1 on page 9-12.
9.20.1 Programming and reading watchpoint registers
A watchpoint register is programmed by shifting data into the EmbeddedICE-RT scan chain
(scan chain 2). The scan chain is a 38-bit shift register comprising:
• a 32-bit data field
• a 5-bit address field
• a read/write bit.
This setup is shown in Figure 9-12.
ARM720T CORE CPU MANUAL
watchpoint 0 watchpoint 1
and
EPSON
9: Debugging Your System
. You can configure
9-33