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9.12
The TAP controller
The TAP controller is a state machine that determines the state of the boundary-scan test
signals DBGTDI and DBGTDO. Figure 9-8 shows the state transitions that occur in the TAP
controller.
Test-Logic Reset
tms=1
Run-Test/Idle
tms=0
Figure 9-8 Test access port controller state transitions
From IEEE Std 1149.1-1990. Copyright 2001 IEEE. All rights reserved.
9.12.1
Resetting the TAP controller
To force the TAP controller into the correct state after power-up, you must apply a reset pulse
to the DBGnTRST signal:
•
When the boundary-scan interface is to be used, DBGnTRST must be driven LOW
and then HIGH again.
•
When the boundary-scan interface is not to be used, you can tie the DBGnTRST
input LOW.
The action of reset is as follows:
1
System mode is selected. This means that the boundary-scan cells do not intercept
any of the signals passing between the external system and the core.
2
The IDCODE instruction is selected.
When the TAP controller is put into the SHIFT-DR state and HCLK is pulsed while
enabled by DBGTCKEN, the contents of the ID register are clocked out of
DBGTDO.
ARM720T CORE CPU MANUAL
0xF
tms=0
tms=1
0xC
tms=1
tms=0
tms=1
EPSON
tms=1
Select-DR-Scan
0x7
tms=0
Capture-DR
0x6
tms=0
Shift-DR
0x2
tms=0
tms=1
Exit1-DR
0x1
tms=1
tms=0
Pause-DR
0x3
tms=0
tms=1
Exit2-DR
tms=0
0x0
tms=1
Update-DR
0x5
tms=0
9: Debugging Your System
Select-IR-Scan
tms=1
0x4
tms=0
tms=1
Capture-IR
0xE
tms=0
Shift-IR
0xA
tms=0
tms=1
Exit1-IR
0x9
tms=1
tms=0
Pause-IR
0xB
tms=0
tms=1
Exit2-IR
0x8
tms=1
Update-IR
0xD
tms=1
tms=0
9-19
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