Table 7-2 Level One Descriptor Bits; Table 7-3 Interpreting Level One Descriptor Bits [1:0] - Epson ARM720T Core Cpu Manual

Revision 4 (amba ahb bus interface version)
Table of Contents

Advertisement

Level one descriptor bit assignments are shown in Table 7-2.
Bits
Section
Coarse
31:20
31:10
19:12
-
11:10
-
9
9
8:5
8:5
4
4
3:2
-
-
3:2
1:0
1:0
The two least significant bits of the level one descriptor indicate the descriptor type as shown
in Table 7-3.
Value
0 0
0 1
1 0
1 1
ARM720T CORE CPU MANUAL

Table 7-2 Level one descriptor bits

Description
Fine
31:12
These bits form the corresponding bits of the
physical address
-
Should Be Zero
-
Access permission bits. Domain access control on
page 7-17 and Fault checking sequence on page
7-19 show how to interpret the access permission
bits
11:9
Should Be Zero
8:5
Domain control bits
4
Must be 1
-
These bits, C and B, indicate whether the area of
memory mapped by this page is treated as
cachable or noncachable, and bufferable or
nonbufferable. (The system is always
write-through.)
3:2
Should Be Zero
1:0
These bits indicate the page size and validity and
are interpreted as shown in Table 7-3

Table 7-3 Interpreting level one descriptor bits [1:0]

Meaning
Description
Invalid
Generates a section translation fault
Coarse page
Indicates that this is a coarse page table
table
descriptor
Section
Indicates that this is a section descriptor
Fine page table
Indicates that this is a fine page table
descriptor
EPSON
7: Memory Management Unit
7-7

Advertisement

Table of Contents
loading

Table of Contents