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6: The Bus Interface
6.4.4
HBURST[2:0]
HBURST[2:0] indicates the type of burst generated by the ARM720T core, as shown in
Table 6-3.
HBURST[2:0]
b000
b001
b101
For more details of burst operation, see the
6.4.5
HPROT[3:0]
HPROT[3:0] is the protection control bus. These signals provide additional information about
a bus access and are primarily intended to enable a module to implement an access permission
scheme.
These signals indicate whether the transfer is:
•
an opcode fetch or data access
•
a privileged-mode access or User-mode access.
For bus masters with a memory management unit, these signals also indicate whether the
current access is cachable or bufferable.
Table 6-4 shows the protection control encodings as produced from the ARM720T core.
HPROT[3]
cachable
-
-
-
-
-
-
0
1
Some bus masters are not capable of generating accurate protection information, so it is
recommended that slaves do not use the HPROT[3:0] signals unless strictly necessary.
6-8
Table 6-3 Burst type encodings
Type
SINGLE
INCR
INCR8
AMBA Specification (Rev 2.0)
Table 6-4 Protection control encodings
HPROT[2]
HPROT[1]
bufferable
privileged
-
-
-
-
-
0
-
1
0
-
1
-
-
-
-
-
EPSON
Description
Single transfer
Incrementing burst of
unspecified length
8-beat incrementing burst
HPROT[0]
Description
data/opcode
0
Opcode fetch
1
Data access
-
User access
-
Privileged access
-
Not bufferable
-
Bufferable
-
Not cachable
-
Cachable
ARM720T CORE CPU MANUAL
.
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