Fault Address And Fault Status Registers; Table 7-9 Priority Encoding Of Fault Status - Epson ARM720T Core Cpu Manual

7: Memory Management Unit
7.5

Fault address and fault status registers

On an abort, the MMU places an encoded 4-bit value, FS[3:0], along with the 4-bit encoded
domain number, in the data FSR, and the MVA associated with the abort is latched into the
FAR. If an access violation simultaneously generates more than one source of abort, they are
encoded in the priority given in Table 7-9.
7.5.1 Fault Status
Table 7-9 describes the various access permissions and controls supported by the data MMU
and details how these are interpreted to generate faults.
Priority Source
Highest Alignment
Translation
Domain
Permission
Lowest External abort on noncachable
nonbufferable access or
noncachable bufferable read
Alignment faults can write either b0001 or b0011 into FS[3:0]. Invalid values in
Note:
domains [3:0] can occur because the fault is raised before a valid domain field has
been read from a page table descriptor. Any abort masked by the priority encoding
can be regenerated by fixing the primary abort and restarting the instruction.
7-16

Table 7-9 Priority encoding of fault status

Size
-
Section
Page
Section
Page
Section
Page
Section
Page
EPSON
Status Domain
b00x1 Invalid
b0101 Invalid
b0111 Valid
b1001 Valid
b1011 Valid
b1101 Valid
b1111 Valid
b1000 Valid
b1010 Valid
ARM720T CORE CPU MANUAL
FAR
MVA of access
causing abort
MVA of access
causing abort
MVA of access
causing abort
MVA of access
causing abort
MVA of access
causing abort