Scan Chains And The Jtag Interface; Figure 9-7 Arm720T Processor Scan Chain Arrangements - Epson ARM720T Core Cpu Manual

9.11

Scan chains and the JTAG interface

There are three JTAG-style scan chains within the ARM720T processor. These enable
debugging and EmbeddedICE-RT programming.
Test Access Port
A JTAG-style
the JTAG specification, see IEEE Standard 1149.1 - 1990
Boundary-Scan Architecture
9.11.1 Scan chain implementation
The three scan paths on the ARM720T processor are referred to as scan chain 1, scan chain 2,
and scan chain 15. They are shown in Figure 9-7.
Debug scan chain 0 is not implemented in the ARM720T processor, but all the control signals
are provided at the macrocell boundary. This enables you to design your own boundary scan
chain wrapper if required.

Figure 9-7 ARM720T processor scan chain arrangements

Scan chain 1
Scan chain 1 provides serial access to the core data bus HRDATA/HWDATA and the
DBGBREAK signal.
There are 33 bits in this scan chain, the order being (from serial data in to out):
• data bus bits 0 through 31
• the DBGBREAK bit (the first to be shifted out).
Scan chain 2
Scan chain 2 enables access to the EmbeddedICE-RT registers. See
9-22 for details.
ARM720T CORE CPU MANUAL
(TAP) controller controls the scan chains. For more details of
.
ARM720T
EmbeddedICE-RT
Scan chain 2
ARM720T TAP controller
(also provides scan chain 0
EPSON
Standard Test Access Port and
ARM720T
processor
System control
control signals)
Test data registers
9: Debugging Your System
processor
Scan chain 15
on page
9-17