Motorola CPU32 Reference Manual page 114

DIVS
DIVSL
Operation:
Assembler
Syntax:
Attributes:
Description:
and and stores the signed result in the destination. The instruction uses one of four
forms.
The word form of the instruction divides a long word by a word. The result is a quotient
in the lower word (least significant 16 bits) and a remainder in the upper word (most
significant 16 bits) of the destination. The sign of the remainder is the same as the sign
of the dividend.
The first long form divides a long word by a long word. The result is a long quotient;
the remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long word.
The result is a long word quotient and a long word remainder.
The third long form divides a long word by a long word. The result is a long word quo-
tient and a long word remainder.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected before instruction completion. If an overflow is
detected, the overflow condition code is set and the operands are unaffect-
ed.
MOTOROLA
4-66
Signed Divide
Destination / Source → Destination
DIVS.W 〈ea〉, Dn32/16 → 16r:16q
DIVS.L 〈ea〉, Dq32/32 → 32q
DIVS.L 〈ea〉, Dr:Dq64/32 → 32r:32q
DIVSL.L 〈ea〉, Dr:Dq32/32 → 32r:32q
Size = (Word, Long)
Divides the signed destination operand by the signed source oper-
INSTRUCTION SET
DIVS
DIVSL
CPU32
REFERENCE MANUAL