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4.3.10
Condition Tests ............................................................................... 4-12
4.4
Instruction Details .................................................................................... 4-13
4.5
Instruction Format Summary ................................................................. 4-170
4.6
Table Lookup and Interpolation Instructions .........................................4-188
4.6.1
Table Example 1: Standard Usage ............................................... 4-188
4.6.2
Table Example 2: Compressed Table ........................................... 4-189
4.6.3
Table Example 3: 8-Bit Independent Variable ...............................4-191
4.6.4
Table Example 4: Maintaining Precision ....................................... 4-192
4.6.5
Table Example 5: Surface Interpolations ...................................... 4-194
4.7
Nested Subroutine Calls ........................................................................ 4-194
4.8
Pipeline Synchronization with the NOP Instruction ...............................4-194
5.1
State Transitions ....................................................................................... 5-1
5.2
Privilege Levels ......................................................................................... 5-1
5.2.1
Supervisor Privilege Level ................................................................. 5-2
5.2.2
User Privilege Level .......................................................................... 5-2
5.2.3
Changing Privilege Level ................................................................... 5-2
5.3
Types of Address Space ........................................................................... 5-3
5.3.1
CPU Space Access .......................................................................... 5-3
5.3.1.1
Type 0000 - Breakpoint .......................................................... 5-4
5.3.1.2
Type 0001 - MMU Access ......................................................5-4
5.3.1.3
Type 0010 - Coprocessor Access ........................................... 5-4
5.3.1.4
Type 0011 - Internal Register Access ..................................... 5-4
5.3.1.5
Type 1111 - Interrupt Acknowledge ........................................ 5-5
6.1
Definition of Exception Processing ............................................................ 6-1
6.1.1
Exception Vectors ............................................................................. 6-1
6.1.2
Types of Exceptions .......................................................................... 6-2
6.1.3
Exception Processing Sequence .......................................................6-3
6.1.4
Exception Stack Frame ..................................................................... 6-3
6.1.5
Multiple Exceptions ........................................................................... 6-4
6.2
Processing of Specific Exceptions ............................................................ 6-5
6.2.1
Reset ................................................................................................. 6-5
6.2.2
Bus Error ...........................................................................................6-6
6.2.3
Address Error .................................................................................... 6-7
6.2.4
Instruction Traps ................................................................................ 6-8
CPU32
REFERENCE MANUAL
TABLE OF CONTENTS
(Continued)
Title
SECTION 5
PROCESSING STATES
SECTION 6
EXCEPTION PROCESSING
Page
MOTOROLA
v
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