Fault Recovery - Motorola CPU32 Reference Manual

ister and program counter are updated from the stack, the active supervisor stack
pointer is incremented by 12, and normal instruction execution resumes.
For a bus fault frame, the format value on the stack is first checked for validity. In ad-
dition, the version number on the stack must match the version number of the proces-
sor that is attempting to read the stack frame. The version number is located in the
most significant byte (bits [15:8]) of the internal register word at location SP + $14 in
the stack frame. The validity check insures that stack frame data will be properly inter-
preted in multiprocessor systems.
If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error
exception is taken. Otherwise, the processor reads the entire frame into the proper in-
ternal registers, de-allocates the stack (12 words), and resumes normal processing.
Bus error frames for faults during exception processing require the RTE instruction to
rewrite the faulted stack frame. If an error occurs during any of the bus cycles required
by rewrite, the processor halts.
If a format error occurs during RTE execution, the processor creates a normal four-
word fault stack frame below the frame that it was attempting to use. If a bus error oc-
curs, a bus-error stack frame will be created. The faulty stack frame remains intact, so
that it may be examined and repaired by an exception handler, or used by a different
type of processor (e.g., an MC68010, MC68020, or a future M68000 processor) in a
multiprocessor system.

6.3 Fault Recovery

There are four phases of recovery from a fault: recognizing the fault, saving the pro-
cessor state, repairing the fault (if possible), and restoring the processor state. Saving
and restoring the processor state are described in the following paragraphs.
The stack contents are identified by the special status word (SSW). In addition to iden-
tifying the fault type represented by the stack frame, the SSW contains the internal pro-
cessor state corresponding to the fault.
15 14 13
TP MV 0 TR
TP BERR frame type
MV MOVEM in progress
TR Trace pending
B1 Breakpoint channel 1 pending
B0 Breakpoint channel 0 pending
RR Rerun write cycle after RTE
RM Faulted cycle was read-modify-write
IN Instruction/other
RW Read/write of faulted bus cycle
LG Original operand size was long word
SIZ Remaining size of faulted bus cycle
FUNC Function code of faulted bus cycle
MOTOROLA
6-14
12 11 10 9
B1 B0 RR
EXCEPTION PROCESSING
8 7 6 5
RM IN RW LG
4 3 2 1
SIZ FUNC
CPU32
REFERENCE MANUAL
0