Data Types - Motorola CPU32 Reference Manual

The program counter (PC) contains the address of the next instruction to be executed
by the CPU32. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate.
The status register (SR) (see Figure 2-3) contains condition codes, an interrupt priority
mask (three bits), and three control bits. Condition codes reflect the results of a previ-
ous operation. The codes are contained in the low byte, or condition code register of
the SR. The interrupt priority mask determines the level of priority an interrupt must
have in order to be acknowledged. The control bits determine trace mode and privilege
level. At user privilege level, only the condition code register is available. At supervisor
privilege level, software can access the full status register.
15 14 13
T1 T0 S
TRACE
ENABLE
SUPERVISOR/USER
STATE
The vector base register (VBR) contains the base address of the exception vector ta-
ble in memory. The displacement of an exception vector is added to the value in this
register to access the vector table.
Alternate function code registers SFC and DFC contain 3-bit function codes. The
CPU32 generates a function code each time it accesses an address. Specific codes
are assigned to each type of access. The codes can be used to select eight dedicated
4G-byte address spaces. The MOVE instructions can use registers SFC and DFC to
specify the function code of a memory address.

2.3 Data Types

Six basic data types are supported:
1. Bits
2. Binary-Coded Decimal (BCD) Digits
3. Byte Integers (8 bits)
4. Word Integers (16 bits)
5. Long-Word Integers (32 bits)
6. Quad-Word Integers (64 bits)
CPU32
REFERENCE MANUAL
SYSTEM BYTE
12 11 10 9
0 0 I2 I1
INTERRUPT
PRIORITY MASK
Figure 2-3 Status Register
ARCHITECTURE SUMMARY
(CONDITION CODE REGISTER)
8 7 6 5
I0 0 0 0
EXTEND
USER BYTE
4 3 2 1
X N Z V
NEGATIVE
ZERO
OVERFLOW
CARRY
MOTOROLA
0
C
2-3