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STOP
Operation:
Assembler
Syntax:
Attributes:
Description:
supervisor portions), advances the program counter to point to the next instruction,
and stops the fetching and executing of instructions. A trace, interrupt, or reset excep-
tion causes the processor to resume instruction execution. A trace exception occurs if
instruction tracing is enabled (T0 = 1, T1=0) when the STOP instruction begins exe-
cution. If an interrupt request is asserted with a priority higher than the priority level
set by the new status register value, an interrupt exception occurs; otherwise, the
interrupt request is ignored. External reset always initiates reset exception process-
ing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
14
13
0
1
0
Instruction Fields:
Immediate field — Specifies the data to be loaded into the status register.
CPU32
REFERENCE MANUAL
Load Status Register and Stop
(Privileged Instruction)
If supervisor state
then Immediate Data → SR; STOP
else TRAP
STOP #〈data〉
Unsized
Moves the immediate operand into the status register (both user and
12
11
10
9
0
1
1
1
IMMEDIATE DATA
INSTRUCTION SET
8
7
6
5
0
0
1
1
STOP
4
3
2
1
1
0
0
1
MOTOROLA
0
0
4-143
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