Instruction Pipeline - Motorola CPU32 Reference Manual

MICROSEQUENCER AND CONTROL
CONTROL STORE
CONTROL LOGIC
ADDRESS
BUS
Figure 8–1 Block Diagram of Independent Resources

8.1.2 Instruction Pipeline

The CPU32 contains a two-word instruction pipeline where instruction opcodes are
decoded. Each stage of the pipeline is initially filled under microsequencer control and
subsequently refilled by the prefetch controller as it empties.
Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus before
stage B empties are temporarily stored in this buffer. Instruction words (instruction op-
eration words and all extension words) are decoded at stage B. Residual decoding and
execution take place in stage C.
Each pipeline stage has an associated status bit that shows whether the word in that
stage was loaded with data from a bus cycle that terminated abnormally.
8.1.3 Bus Controller Resources
The bus controller consists of the instruction prefetch controller, the write-pending
buffer, and the microbus controller. These three resources transact all reads, writes,
and instruction prefetches required for instruction execution.
MOTOROLA
8-2
INSTRUCTION PIPELINE
STAGE
C
EXECUTION UNIT
PROGRAM
COUNTER
SECTION
SECTION
WRITE-PENDING PREFETCH
BUFFER CONTROLLER
MICROBUS
CONTROLLER
BUS CONTROL
SIGNALS
INSTRUCTION EXECUTION TIMING
STAGE STAGE
B A
DATA
DATA
BUS
CPU32
REFERENCE MANUAL