Command-Sequence-Diagram Example - Motorola CPU32 Reference Manual

The "not ready" response can be ignored unless a memory bus cycle
is in progress. Otherwise, the CPU can accept a new serial transfer
with eight system clock periods.
In the third cycle, the development system supplies the low-order 16 bits of a memory
address. The CPU always returns the "not ready" response in this cycle. At the com-
pletion of the third cycle, the CPU initiates a memory read operation. Any serial trans-
fers that begin while the memory access is in progress return the "not ready" response.
Results are returned in the two serial transfer cycles following the completion of mem-
ory access. The data transmitted to the CPU during the final transfer is the opcode for
the following command. Should a memory access generate either a bus or address
error, an error status is returned in place of the result data.
COMMANDS TRANSMITTED TO THE CPU
COMMAND CODE TRANSMITTED DURING THIS CYCLE
READ (LONG)
???
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY CPU
RESULTS FROM PREVIOUS COMMAND
RESPONSES FROM THE CPU
Figure 7-10 Command-Sequence-Diagram Example
CPU32
REFERENCE MANUAL
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
MS ADDR LS ADDR
"NOT READY" "NOT READY"
XXX
NEXT CMD
"ILLEGAL" "NOT READY"
DATA UNUSED FROM
THIS TRANSFER
DEVELOPMENT SUPPORT
NOTE
LOW-ORDER 16 BITS OF MEMORY ADDRESS
NONSERIAL-RELATED ACTIVITY
READ
MEMORY
LOCATION
HIGH- AND LOW-ORDER
16 BITS OF RESULT
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
NEXT
COMMAND
CODE
XXX
"NOT READY"
XXX NEXT CMD
MS RESULT LS RESULT
XXX NEXT CMD
BERR/AERR "NOT READY"
SEQUENCE TAKEN IF BUS ERROR
OR ADDRESS ERROR OCCURS ON
MEMORY ACCESS
MOTOROLA
7-13