Shift And Rotate Instructions; Shift And Rotate Operations - Motorola CPU32 Reference Manual

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4.3.5 Shift and Rotate Instructions

The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and
LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL in-
structions perform rotate (circular shift) operations, with and without the extend bit. All
shift and rotate operations can be performed on either registers or memory.
Register shift and rotate operations shift all operand sizes. The shift count may be
specified in the instruction operation word (to shift from 1 to 8 places) or in a register
(modulo 64 shift count).
Memory shift and rotate operations shift word-length operands one bit position only.
The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/
rotate instructions is enhanced so that use of the ROR and ROL instructions with a
shift count of eight allows fast byte swapping. Table 4-5 is a summary of the shift and
rotate operations.
Instruction
ASL
ASR
LSL
LSR
ROL
ROR
ROXL
ROXR
SWAP
CPU32
REFERENCE MANUAL
Table 4-4 Logic Operations
〈ea〉
8, 16, 32
Table 4-5 Shift and Rotate Operations
Syntax Operand Size
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn, Dn 8, 16, 32
#〈data〉, Dn 8, 16, 32
〈ea〉
16
Dn 16
INSTRUCTION SET
Source – 0, to set condition codes
Operation
X/C
X/C
0
C
C
X
MSW
0
X/C
0
X/C
C
X
C
LSW
MOTOROLA
4-9