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LSL, LSR
Condition Codes:
X
N
Z
*
*
*
X
Set according to the last bit shifted out of the operand. Unaffected for a shift
count of zero.
N
Set if the result is negative. Cleared otherwise.
Z
Set if the result is zero. Cleared otherwise.
V
Always cleared.
C
Set according to the last bit shifted out of the operand. Cleared for a shift count
of zero.
Instruction Format (Register Shifts):
15
14
13
1
1
1
Instruction Fields (Register Shifts):
Count/Register field — Specifies shift count or register that contains shift count:
If i/r = 0, this field contains the shift count. The values one to seven represent
counts of one to seven; value of zero represents a count of eight.
If i/r = 1, this field specifies the data register that contains the shift count (mod-
ulo 64).
dr field — Specifies the direction of the shift:
0 — Shift right
1 — Shift left
Size field — Specifies the size of the operation:
00 — Byte operation
01 — Word operation
10 — Long operation
i/r field:
If i/r = 0, specifies immediate shift count.
If i/r = 1, specifies register shift count.
Register field — Specifies a data register to be shifted.
CPU32
REFERENCE MANUAL
Logical Shift
V
C
0
*
12
11
10
9
0
COUNT/REGISTER
INSTRUCTION SET
8
7
6
5
dr
SIZE
i/r
LSL, LSR
4
3
2
1
0
1
REGISTER
MOTOROLA
0
4-87
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