Motorola CPU32 Reference Manual page 330

Single Operand Instruction Timing 8-18
Six-Word Stack Frame, Normal 6-22
Sizing, Dynamic Bus 6-16, 6-23
Software Breakpoints 6-8
Software Fault Recovery 6-19
Space Formats 5-4
Type 0000 - Breakpoint 5-4
Type 0001 - MMU Access 5-4
Type 0010 - Coprocessor Access 5-4
Type 0011 - Internal Register Access 5-4
Type 1111 - Interrupt Acknowledge 5-5
Special Addressing Modes 3-7
Special-Purpose MOVE Instruction Timing 8-14
Stack
Frames 6-3, 6-21
Supervisor 2-2, 3-15
System 3-16
User 2-2, 3-15
State Transition 5-1
Status Register 2-3
Subroutine Calls, Nested 4-194
Supervisor Privilege Level 5-2
Surface Interpolation 4-188, 4-194
Synchronization, Pipeline with NOP 4-194
System
Control Instructions 4-11
Stack 3-16
–T–
Table Lookup and Interpolation 4-187
Examples
8-Bit Independent Variable 4-191
Compressed Table 4-190
Maintaining Precision 4-192
Standard Usage 4-188
Surface Interpolations 4-194
Instruction, Using the 4-188
Tests, Condition 4-12
Timing Examples
Branch Instructions 8-8
Execution Overlap 8-7
Negative Tails 8-9
Timing Tables 8-10
Arihmetic/Logic Instructions 8-15
Binary-Coded Decimal/Extended Instructions 8-18
Bit Manipulation Instructions 8-20
Calculate Effective Address (CEA) 8-13
Conditional Branch Instructions 8-20
Control Instructions 8-21
Exception-Related Instructions 8-21
CPU32
REFERENCE MANUAL
Fetch Effective Address (FEA) 8-10
Immediate Arithmetic/Logic Instructions 8-17
MOVE Instruction 8-14
Save and Restore Operations 8-22
Shift/Rotate instructions 8-19
Single Operand instructions 8-18
Special-Purpose MOVE Instruction 8-14
Trace on Instruction Execution 6-11, 7-1
Unimplemented instruction Emulation 6-9, 7-1
Unimplemented Instructions 4-2, 6-9
User Privilege Level 5-2
User Stacks 3-16
Vector Base Register 1-3, 2-3, 6-1
Vectors, Exception 6-1
Virtual Memory 1-2
Write Pending Buffer 8-3
INDEX
–U–
–V–
–W–
MOTOROLA
I-4