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MULU
Operation:
Assembler
Syntax:
Attributes:
Description:
In the word form, the multiplier and multiplicand are both word operands, and the
result is a long word operand. A register operand is the low-order word; the upper
word of the register is ignored. All 32 bits of the product are saved in the destina-
tion data register.
In the long form, the multiplier and multiplicand are both long word operands, and
the result is either a long word or a quad word. The long word result is the low-
order 32 bits of the quad word result; the high-order 32 bits of the product are dis-
carded.
Condition Codes:
X
N
Z
—
*
*
X
Not affected.
N
Set if the result is negative. Cleared otherwise.
Z
Set if the result is zero. Cleared otherwise.
V
Set if overflow. Cleared otherwise.
C
Always cleared.
Overflow (V=1) can occur only when multiplying 32-bit operands to
yield a 32-bit result. Overflow occurs if any of the high-order 32 bits
of the quad word product are not equal to zero.
MOTOROLA
4-110
Unsigned Multiply
Source ∗ Destination → Destination
MULU.W 〈ea〉, Dn16x16 → 32
MULU.L 〈ea〉, Dl32x32 → 32
MULU.L 〈ea〉, Dh:Dl32x32 →64
Size = (Word, Long)
Multiplies two unsigned operands yielding an unsigned result.
V
C
*
0
INSTRUCTION SET
NOTE
MULU
CPU32
REFERENCE MANUAL
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