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15
14
12
D/A
REGISTER
D/A:
0 = Data Register Select
1 = Address Register Select
W/L
0 = Word-Sized Operation
1 = Long-Word-Sized Operation
15
14
12
D/A
REGISTER
D/A:
0 = Data Register Select
1 = Address Register Select
W/L
0 = Word-Sized Operation
1 = Long-Word-Sized Operation
SCALE:
00 = Scale Factor 1 (Compatible with MC68000)
01 = Scale Factor 2 (Extension to MC68000)
10 = Scale Factor 4 (Extension to MC68000)
11 = Scale Factor 8 (Extension to MC68000)
Figure 3-6 M68000 Family Address Extension Words
The encoding for SCALE used by the CPU32 and the MC68020 is a compatible ex-
tension of the M68000 architecture. A value of zero for SCALE is the same encoding
for both extension words; thus, software that uses this encoding is both upward and
downward compatible across all processors in the product line. However, the other
values of SCALE are not found in both extension formats; therefore, while software
can be easily migrated in an upward compatible direction, only nonscaled addressing
is supported in a downward fashion. If the MC68000 were to execute an instruction
that encoded a scaling factor, the scaling factor would be ignored and would not ac-
cess the desired memory address.
3.7 Other Data Structures
In addition to supporting the array data structure with the index addressing mode,
M68000 processors also support stack and queue data structures with the address
register indirect postincrement and predecrement addressing modes. A stack is a last-
in-first-out (LIFO) list; a queue is a first-in-first-out (FIFO) list. When data is added to a
stack or queue, it is pushed onto the structure; when it is removed, it is "popped", or
pulled, from the structure. The system stack is used implicitly by many instructions;
user stacks and queues may be created and maintained through use of addressing
modes.
3.7.1 System Stack
Address register 7 (A7) is the system stack pointer (SP). The SP is either the supervi-
sor stack pointer (SSP) or the user stack pointer (USP), depending on the state of the
S bit in the status register. If the S bit indicates the supervisor state, the SSP is the SP,
and the USP cannot be referenced as an address register. If the S bit indicates the
user state, the USP is the active SP, and the SSP cannot be referenced. Each system
CPU32
DATA ORGANIZATION AND ADDRESSING CAPABILITIES
REFERENCE MANUAL
MC6800/MC68008/MC68010 ADDRESS EXTENSION WORD
11
10
9
W/ L
0
0
CPU32/MC68020 EXTENSION WORD
11
10
9
W/ L
SCALE
8
7
0
DISPLACEMENT INTEGER
8
7
0
DISPLACEMENT INTEGER
0
0
MOTOROLA
3-15
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